1. Field of the Invention
The present invention relates to a level shifter circuit, and more particularly, to a level shifter circuit requiring a smaller circuit area.
2. Description of the Prior Art
Level shifter circuits are applied between two digital circuits in order to shift a voltage level of an input signal to a different output level. In general, the voltage level defines the logic value of the signal (ex: logic value 1 or 0). Different digital circuits have different ways to define the logic values. For example, if the voltage level of the signal is larger than 2.5V in the first digital circuit, the logic value of the signal is 1. However, in another digital circuit, if the voltage level of the signal is larger than 5V, the logic value of the signal is 1.
The same signal can therefore have different logic values in different digital circuits. For example, a signal having a 2.5V voltage level can have a corresponding logic value as 1 in a first digital circuit, while in a second digital circuit, the logic value may be 0. Obviously, if the signal is not level-shifted before being inputted from the first digital circuit to the second digital circuit, the different logic value definitions between the two digital circuits may cause errors, resulting in further operational errors for the whole circuit.
Therefore, a level shifter circuit is used to shift voltage level of a signal between digital circuits to solve the above-mentioned problem of different logic value definitions. Using the above example for instance, the level shifter circuit can shift a 2.5 V voltage level of the signal in the first digital circuit to a 5V voltage level for the second circuit. As a result, when the signal is outputted into the second digital circuit, the 5V voltage level of signal is correctly judged as 1. As known to those skilled in this art, level shifter circuits are applied in various circuits, including signal exchanging between a chip and an external circuit or between internal and external circuits of a liquid crystal display (LCD) panel.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a two-to-one, six bit digital-to-analog converter (DAC) 110 using previously described level shifter circuits 120. In this example, the digital-to-analog converter 110 supports 64 different outputs, and is implemented by six stages of two-to-one switches. First, a decoder 130 receives a six-bit digital signal and converts it into input signals I0, I0b, I1, I1b, I2, I2b, I3, I3b, I4, I4b, I5, I5b, for the level shifter circuits 120. Because the voltage levels of the input signals I0˜I5, I0b˜I5b are lower, the inner switches of the digital-to-analog converter 110 can't be controlled by these input signals I0˜I5, I0b˜I5b. The level shifter circuits 120, therefore, are utilized to shift the voltage levels of the input signals, in order to generate the output signals Q0˜Q5, Q0b˜Q5b that can turn on the inner switches of the digital-to-analog converter 110. Furthermore, a switch from every two switches in each stage turns due to control signals Q0˜Q5, Q0b˜Q5b from the level shifter circuits 120. After propagation through six stages of switches, the digital-to-analog converter 110 is able to select one of a plurality of reference voltages (ref1, ref2, . . . , ref64) as an analog voltage output.
Please note in the above example, the signal Ixb is an inverted signal from Ix, and the level shifter circuits 120 output signals Q0˜Q5, Q0b˜Q5b. The circuit designer decides what kind of single as a control voltage of each inner switch. For example, if the inner switches of the digital-to-analog converter 110 are implemented by NMOS transistors, the circuit designer can use the output signals Q0˜Q5 to control the NMOS switches. If the inner switches of the digital-to-analog converter 110 are implemented by PMOS transistors, the circuit designer can use the inverted output signals Q0˜Q5 to control the PMOS switches.
Please refer FIG. 2. FIG. 2 is a detailed circuit diagram of the level shifter circuit 120 in FIG. 1. As FIG. 2 shows, the level shifter circuit 120 includes four transistors (i.e., level shifter units) m1˜m4. The gates of the PMOS transistors m1 and m2 are coupled to the opposing transistors drain. The gates of the NMOS transistors m3 and m4 are the input ends of the level shifter circuit 120, and the drains are the output ends. The control signals I0 and I0b inputted to the input ends control the ON/OFF status of the PMOS transistors m1 and m2 to generate the control signals Q0 and Q0b at the output ends.
However, the above level shifter circuit 120 has its shortcomings. First, the level shifter circuit 120 must output the control signal having a high voltage level. Therefore, the inside components almost are high voltage components for handling high voltages. This requires the sources and drains of the inner transistors to occupy a larger area, further increasing production costs. The transistors of the above level shifter unit 120 would otherwise be coupled to each other in a cross-coupling configuration. When the control signals I0 and I0b at the input ends have level transition (ie. a transition from a high voltage level to a low one or from a low voltage level to a high one), the two separate routes of the level shifter circuit 120 generate a huge transient current, respectively.
In addition, the digital-to-analog converter 110 in FIG. 1 adopts a two-to-one architecture, and the total amount of inner switches for the six stages are 64+32+16+8+4+2=126 pieces. As known to one in the related art, the inner high voltage switches occupy an excessive area. The conventional solution is to utilize other architectures. Please refer to FIG. 3. FIG. 3 is a schematic diagram of a prior art four-to-one, six bit digital-to-analog converter 310. Obviously, because the four-to-one architecture is implemented, the digital-to-analog converter 310 only needs four stages, and the total amount of the inner switches decrease to 64+16+4=84 pieces, decreasing the consuming area.
Unfortunately, the digital-to-analog converter 310 needs more level shifter circuits 120 to shift voltage levels of control signals for the switches of every stage. As FIG. 3 shows, the amount of the level shifter circuits 120 becomes twice the original amount. Moreover, the inside of the level shifter circuit 120 is made up by high voltage components, so the increased amount of level shifter circuits 320 increases the occupied area. This may not be a satisfactory solution for a manufacturer of digital-to-analog converters desiring a smaller circuit area.